Automating Production of Run-Time Recon gurable Designs

This paper describes a method that automates a key step in producing run-time recon gurable designs: the identi cation and mapping of recongurable regions. In this method, two successive circuit con gurations are matched to locate the components common to them, so that recon guration time can be minimized. The circuit congurations are represented as a weighted bipartite graph, to which an e cient matching algorithm is applied. Our method, which supports hierarchical and library-based design, is deviceindependent and has been tested using Xilinx 6200 FPGAs. A number of examples in arithmetic, pattern matching and image processing are selected to illustrate our approach.